📝 About Me

By R Santhosh Singh

R Santhosh Singh 💻✨

Hello, I’m R Santhosh Singh, a passionate M.Tech student in VLSI Design at Vellore Institute of Technology (VIT), Vellore 🎓. My journey is deeply rooted in the fascinating world of micro and nano electronics, with a strong focus on ASIC design, physical design flows, and VLSI verification methodologies.

What I’m Working On:

🔧 Project: I’m currently designing and implementing a 32-bit 5-stage pipelined RISC processor using Xilinx Vivado. This project reflects my passion for cutting-edge VLSI technologies and my love for system-level design challenges ⚙️.

My Expertise:

📚 Beyond academics, I have hands-on experience working on physical design projects using Synopsys ICC2. I specialize in:

  • PnR flow
  • STA (Static Timing Analysis)
  • DFT (Design for Testability)

🛠️ I’m also proficient in various EDA tools, including:

  • Synopsys VCS
  • Design Compiler
  • Cadence Virtuoso

🚀 Languages: My technical skills include Verilog HDL, SystemVerilog, and a basic understanding of UVM for verification.

Always Learning:

🌱 I’m constantly looking for opportunities to grow and apply my skills in real-world environments through internships. I’m eager to collaborate with VLSI professionals to learn, innovate, and contribute to transformative projects in digital IC design, ASIC, DFT, or VLSI verification 🔬.

Contact Information:

📧 Email: santhoshrajputhsingh@gmail.com
📞 Phone: +91-9100256423
🔗 LinkedIn: linkedin.com/in/santhoshrajputh

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Part- 1: Step-by-Step Guide to Building a RISC-V Processor from Scratch

By R Santhosh Singh
🌟 Introduction to RISC-V Architecture Building your own processor might sound challenging, but with the right guidance, it's not only possible—it’s fun! 😃 In this guide, we’ll walk you through the steps to build a simple RISC-V processor from scratch. RISC-V, an open-source instruction set architecture (ISA), is gaining popularity among engineers and hobbyists because of its flexibility and transparency. Unlike proprietary architectures, RISC-V allows complete freedom to explore, modify, and build without licensing restrictions. Whether you're new to computer architecture or an enthusiast, this guide will help you step by step. By the end, you’ll have a working RISC-V processor and a solid understanding of how processors function at a fundamental level. Ready? Let's get started! 🔧💡 🧠 What is RISC? - Reduced Instruction Set Computing RISC stands for Reduced Instruction Set Computing. The concept is simple: keep the instruction set small and efficient so the processor wo...
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Part- 2: Understanding the RISC-V Core: The 5-Stage Pipeline Explained

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A  RISC-V core  follows a classic  5-stage pipeline design . This approach processes instructions efficiently by breaking them down into smaller, manageable steps. Each stage handles a specific part of instruction execution, allowing multiple instructions to be processed simultaneously, boosting overall performance. Fig: Pipelined processor with hazard handling Let’s dive into these five stages: 1️⃣ Instruction Fetch (IF) Stage Objective : Fetch instructions from memory. Key Components : Program Counter (PC) Instruction Memory Tasks : Increment the PC. Fetch the instruction from memory using the current PC. 2️⃣ Instruction Decode (ID) Stage Objective : Decode the fetched instruction and read register values. Key Components : Register File (holds general-purpose registers) Control Unit (generates control signals) Tasks : Decode the opcode and control signals. Read source registers from the register file. 3️⃣ Execute (EX) Stage Objective : Perform ALU operations, com...
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